The present disclosure relates to Complementary Metal Oxide Semiconductor (“CMOS”) integrated circuits and, more particularly, to CMOS implementations of Static Random Access Memories (“SRAM”), digital logic, and related methods for reducing parasitic leakage currents in memory and logic elements.
FIG. 1 illustrates a conventional CMOS SRAM storage cell indicated generally by the reference numeral 100 [1]. As shown in the figure, various parasitic leakage current paths exist between VDD and ground through the various devices. Paths in the solid line represent leakage through the gate nodes of the MOS devices, while subthreshold device source-to-drain leakage is represented by the dotted lines in the figure. As technology scales to deep submicron dimensions, these leakage currents can constitute a significant portion of total power during both standby and active modes. The gate leakage component leakage is a strong function of voltage potential between the gate and either the device source or drain terminal. The subthreshold leakage current is a strong function of device threshold voltage (Vt) and drain-to-source voltage potential, which modulates the Drain-Induced-Barrier Lowering effect (DIBL). [1] “A Novel Powering-down Scheme for Low Vt CMOS Circuits”, Kouichi Kumagai, Hiroaki Iwaki, Hiroshi Yoshida, Hismitsu Suzuki, Takashi Yamada, Susumu Kurosawa, 1998 Symposium on VLSI Circuits Technical Digest, IEEE, pp. 44–45.
FIG. 2 illustrates a conventional technique to dynamically reduce the supply voltage across a logic circuit during standby mode by interrupting the power supply and ground connections of an integrated circuit by a low leakage MOS switch (MPSW and MNSW), indicated generally by the reference numeral 200 [2]. The diodes DN and DP are added to the circuit to reduce and clamp the supply voltage potential to a lower voltage while the circuit is in a standby mode. [2] “Standby Power Management for a 0.18 um Microprocessor”, L. T. Clark, S. Demmons, N. Deutscher, F. Ricci, Proceedings of 2002 International Symposium on Low Power Electronics and Design, Monterey Calif., ACM, pp. 7–12.
The conventional technique illustrated in 200 has problems for voltage scaled devices. The diode is constructed by a P/N junction, which maintains a voltage drop of approximately 0.6V during normal conduction mode. If the supply voltage VDD is normally at 1.0V or less, the remaining small voltage (1.0V−0.6V=0.4V) can cause problems in maintaining the state of the circuit in the presence of noise. It also limits the amount the normal supply voltage can scale to less than the diode built-in potential of 0.6V. Another drawback of this approach is that it is not possible to control the diode voltage drop electronically to adjust the voltage potential across the internal circuits during the standby state because it is fixed by the physical limits of the diode characteristics.
This problem may be solved by using a complex voltage regulator, which uses a reference voltage to determine the virtual ground potential during standby mode. Such a voltage regulator, however, consumes chip area and is centrally located on the chip. The regulator must supply enough sink current to safely clamp the virtual VSS node in modes when the leakage current can be very high, such as under high temperature operation. Distribution of the Virtual VSS node must be done using wiring resources and can be inefficient for use in localized areas of the chip controlled independently.
FIG. 3 illustrates an example of a conventional circuit used to reduce the leakage current during standby mode using a complex regulator, and indicated generally by the reference numeral 300. In the circuit 300, the VSS ground connection is interrupted by the MOS switch M5 during standby mode, while an integrated voltage regulator is used to clamp and hold the floating VSS potential to a higher elevated voltage. During this mode, the PFET Nwell body connection is shorted to an externally generated supply that is higher than the normal VDD connection (IO VDD). This reduces the overall voltage potential across the microprocessor core circuit and reverse well biases both the PFET and NFET devices.